An SDRAM, shown in block diagram in FIG. 1 typically operates as follows, with reference to the signal timing diagram shown in FIG. 2. A clock input terminal 1 receives a clock input signal CLK. The remainder of the SDRAM is represented by the memory array and support circuitry block 3. The clock signal arriving at the clock input terminal 1 is buffered inside the SDRAM, represented by the receiver 5 and buffer 6, and is distributed to internal circuitry of the SDRAM.
A signal at the output of the memory array and support circuitry 3 is applied to output buffers, represented by output buffer 8, which is enabled by the clock signal to drive data onto data terminals 10 of the SDRAM. However, due to the delays caused by the internal buffering and the interconnect wire on the integrated circuit chip that distributes the clock signal, the clock signal arrives at the enable terminal of the buffers delayed from the clock input signal. This delayed clock signal is illustrated in FIG. 2 as signal ICLK.
Assuming that the system is responsive to the rising edge of the clock signal, the delay between the rising edges is shown in FIG. 2 as internal clock skew 12. This clock skew can be a significant fraction of the clock period if the part is driven with a high frequency clock. The clock skew typically determines the maximum speed of the part. As the operating frequency of the part increases, as determined by the clock frequency, the clock skew delay causes enabling of the output buffer 8 too late relative to the next rising clock edge and the valid data at the output data terminals 10 will appear too late for the receiving chip.
Prior to the present invention, there we either of two solutions used to deal with this problem: (a) making the clock buffer circuitry between the clock input terminal 1 and the output buffer circuit enable terminal as fast as possible, and (b) using a phase locked loop (PLL) to drive the enable terminal of the output buffer.
Implementing the first solution results in a limit to the operating frequency of the part. There will always be a limit to the operating frequency of the part, because there will always be significant delay associated with the clock buffer and distribution circuitry and delays introduced by parasitic resistance and capacitance of the interconnection conductors used to distribute the buffered clock signal to the output buffers, which is evident from FIG. 1. Thus as shown in FIG. 2, after the read command to the memory array circuitry 3 from the address and control input of the memory array, to output data to the output buffers 8, there must be a delay 12 until valid data is output to the data terminals 10, as indicated by the timing diagram DQ. This time is the sum of the internal clock skew from the rising edge of the clock input signal CLK to the rising edge of the delayed clock signal ICLK, and the time from the rising edge of the clock signal ICLK to the time that valid data is output on the output terminals 10 caused by the output buffer delay after it has been clocked by the ICLK signal.
The second solution provides considerable improvement over the first. An on chip oscillator is used in a phase locked loop (PLL) which is synchronized with the input clock signal. The internal clock signal can be either multiplied in frequency or adjusted to remove internal clock skew as much as possible.
A system implementing the second solution is shown in FIG. 3, and a corresponding timing diagram is shown in FIG. 4. A PLL 15 is fed by the input clock signal from receiver 5, as well as by a feedback signal on conductor 17 derived from the interconnection conductor which distributes the output buffer enable clock signal. The later signal is received from the output of the PLL via the internal buffering circuitry represented by buffer 6.
Thus the already buffered (and delayed) clock signal is applied to the PLL and is compared with the input clock signal. Since the operation of the PLL is to synchronize the two signals, the clock signal to be distributed to the enable inputs of the output buffers, represented by the timing diagram ICLK in FIG. 4, is made as close as possible in timing to the input clock signal. The internal clock skew is thus minimized, as illustrated by skew time 19 shown in FIG. 4. Thus the output buffer is enabled much closer to the clock edge that is received by the part and valid data appears sooner relative to the clock edge, and thus allowing higher frequency operation of the part. This is shown by access time 21, which it may be seen is much shorter than access time 12 resulting from the first solution.
However it has been found that the PLL solution also suffers from problems. It is complex, requiring an on-chip oscillator with feedback control of the frequency depending on the monitored status of the on-chip oscillator relative to the input clock. It requires significant stand-by power due to its extra circuitry, and it requires considerable start-up time for the on-chip oscillator to synchronize and lock to the input clock frequency. It also requires use of an analog oscillator in a digital circuit, which requires significantly different and complex fabrication techniques.